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M74HC597
8 BIT LATCH/SHIFT REGISTER
s
s
s
s
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HIGH SPEED : fMAX = 50 MHz (TYP.) at VCC = 6V LOW POWER DISSIPATION: ICC =4A(MAX.) at TA=25C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL WIDE OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 597
DIP
SOP
TSSOP
ORDER CODES
PACKAGE DIP SOP TSSOP TUBE M74HC597B1R M74HC597M1R T&R M74HC597RM13TR M74HC597TTR
DESCRIPTION The M74HC597 is an high speed CMOS 8 BIT PIPO SHIFT REGISTER fabricated with silicon gate C2MOS technology. This devices comes in a 16-pin package and consist of an 8-bit storage latch feeding a parallel in, serial out 8-bit shift register. Both the storage
register and shift register have positive edge triggered clocks. The shift register also has direct load (from storage) and clear inputs. All inputs are equipped with protection circuits against static discharge and transient excess voltage.
PIN CONNECTION AND IEC LOGIC SYMBOLS
July 2001
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M74HC597
INPUT AND OUTPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 9 10 11 12 13 10 15, 1, 2, 3, 4, 5, 6, 7 8 16 SYMBOL QH' SCLR SCK RCK SLOAD SI A to H GND Vcc NAME AND FUNCTION Serial Data Outputs Asynchronous Reset Input (Active LOW) Shift Clock Input (LOW to HIGH Edge-triggered) Storage Clock Input (LOW to HIGH Edge-triggered) Parallel Data Input (Active Low) Serial Data Input Parallel Data Inputs Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUTS OUTPUT SI X X L H X X X
X : Don't Care
SCK X X
SCLR L H H H H
SLOAD H L H H H X X
RCK X X X X X S.R. IS CLEARED TO "L" INPUT REGISTER DATA IS STORED INTO S.R. FIRST STAGE OF S.R. BECOMES "L" OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY FIRST STAGE OF S.R. BECOMES "H" OTHER STAGES STORE THE DATA OF PREVIOUS STAGE, RESPECTIVELY STATE OF S.R. IS NOT CHANGED INPUT DATA ON A ~ H LINE IS STORED INTO INPUT REGISTER STORAGE REGISTER STATE IS NOT CHANGED
X X
X X
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M74HC597
LOGIC DIAGRAM
This logic diagram has not be used to estimate propagation delays
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M74HC597
TIMING CHART
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 25 50 500(*) -65 to +150 300 Unit V V V mA mA mA mA mW C C
ICC or IGND DC VCC or Ground Current
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied (*) 500mW at 65 C; derate to 300mW by 10mW/C from 65C to 85C
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M74HC597
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top tr, tf Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time VCC = 2.0V VCC = 4.5V VCC = 6.0V Parameter Value 2 to 6 0 to VCC 0 to VCC -55 to 125 0 to 1000 0 to 500 0 to 400 Unit V V V C ns ns ns
DC SPECIFICATIONS
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 VOL Low Level Output Voltage 2.0 4.5 6.0 4.5 6.0 II ICC Input Leakage Current Quiescent Supply Current 6.0 6.0 IO=-20 A IO=-20 A IO=-20 A IO=-4.0 mA IO=-5.2 mA IO=20 A IO=20 A IO=20 A IO=4.0 mA IO=5.2 mA VI = VCC or GND VI = VCC or GND TA = 25C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.18 5.68 2.0 4.5 6.0 4.31 5.8 0.0 0.0 0.0 0.17 0.18 0.1 0.1 0.1 0.26 0.26 0.1 4 1.9 4.4 5.9 4.13 5.63 0.1 0.1 0.1 0.33 0.33 1 40 Typ. Max. Value -40 to 85C Min. 1.5 3.15 4.2 0.5 1.35 1.8 1.9 4.4 5.9 4.10 5.60 0.1 0.1 0.1 0.40 0.40 1 80 A A V V Max. -55 to 125C Min. 1.5 3.15 4.2 0.5 1.35 1.8 Max. V Unit
VIH
High Level Input Voltage Low Level Input Voltage High Level Output Voltage
VIL
V
VOH
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M74HC597
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition Symbol Parameter VCC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 TA = 25C Min. Typ. 30 8 7 78 20 16 90 24 20 80 22 18 112 30 24 12 48 50 20 7 4 25 7 5 48 12 10 20 5 4 20 5 4 Max. 75 15 13 145 29 25 175 35 30 175 35 30 210 42 36 4.8 24 28 75 15 13 75 15 13 100 20 17 75 15 13 75 15 13 0 0 0 75 15 13 95 19 16 95 19 16 125 25 21 95 19 16 95 19 16 0 0 0 95 19 16 Value -40 to 85C Min. Max. 95 19 16 180 36 31 220 44 37 220 44 37 265 53 45 4.0 20 24 110 22 19 110 22 19 150 30 26 110 22 19 110 22 19 0 0 0 115 23 20 -55 to 125C Min. Max. 115 23 20 220 44 37 265 53 45 265 53 45 315 63 54 ns Unit
tTLH tTHL Output Transition Time tPLH tPHL Propagation Delay Time (SCK - QH') tPLH tPHL Propagation Delay Time (SCLR - QH') tPLH tPHL Propagation Delay Time (SLOAD - QH') tPLH tPHL Propagation Delay Time (RCK- QH') fMAX Maximum Clock Frequency Minimum Pulse Width (SCK, RCK)
ns
ns
ns
SLOAD = "L" 6.0 30 35
ns
MHz
tW(H) tW(L) tW(L)
ns
ts
Minimum Pulse Width (SCLR, SLOAD) Minimum Set-up Time (RCK SLOAD) Minimum Set-up Time (SI, SCK) Minimum Set-up Time (PI, RCK) Minimum Hold Time Minimum Removal Time
ns
ns
ts
ns
ts
ns
th
ns
tREM
12 4 3
ns
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M74HC597
CAPACITIVE CHARACTERISTICS
Test Condition Symbol Parameter VCC (V) 5.0 5.0 TA = 25C Min. Typ. 5 60 Max. 10 Value -40 to 85C Min. Max. 10 -55 to 125C Min. Max. 10 pF pF Unit
CIN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
1) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
TEST CIRCUIT
CL = 50pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
WAVEFORM 1 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME(f=1MHz; 50% duty cycle)
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WAVEFORM 2 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)
WAVEFORM 3 : MINIMUM PULSE WIDTH AND REMOVAL TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 4 : MINIMUM SETUP AND HOLD TIME (f=1MHz; 50% duty cycle)
WAVEFORM 5 : PROPAGATION DELAY, MINIMUM PULSE WIDTH, REMOVAL TIME (f=1MHz; 50% duty cycle)
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WAVEFORM 6: MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)
WAVEFORM 7: INPUT WAVEFORM (f=1MHz; 50% duty cycle)
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M74HC597
Plastic DIP-16 (0.25) MECHANICAL DATA
mm. DIM. MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.27 8.5 2.54 17.78 7.1 5.1 0.130 0.050 0.51 0.77 0.5 0.25 20 0.335 0.100 0.700 0.280 0.201 1.65 TYP MAX. MIN. 0.020 0.030 0.020 0.010 0.787 0.065 TYP. MAX. inch
P001C
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M74HC597
SO-16 MECHANICAL DATA
DIM. A a1 a2 b b1 C c1 D E e e3 F G L M S 3.8 4.6 0.5 9.8 5.8 1.27 8.89 4.0 5.3 1.27 0.62 8 (max.) 0.149 0.181 0.019 10 6.2 0.35 0.19 0.5 45 (typ.) 0.385 0.228 0.050 0.350 0.157 0.208 0.050 0.024 0.393 0.244 0.1 mm. MIN. TYP MAX. 1.75 0.2 1.65 0.46 0.25 0.013 0.007 0.019 0.003 MIN. inch TYP. MAX. 0.068 0.007 0.064 0.018 0.010
PO13H
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M74HC597
TSSOP16 MECHANICAL DATA
mm. DIM. MIN. A A1 A2 b c D E E1 e K L 0 0.45 0.60 0.05 0.8 0.19 0.09 4.9 6.2 4.3 5 6.4 4.4 0.65 BSC 8 0.75 0 0.018 0.024 1 TYP MAX. 1.2 0.15 1.05 0.30 0.20 5.1 6.6 4.48 0.002 0.031 0.007 0.004 0.193 0.244 0.169 0.197 0.252 0.173 0.0256 BSC 8 0.030 0.004 0.039 MIN. TYP. MAX. 0.047 0.006 0.041 0.012 0.0089 0.201 0.260 0.176 inch
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
0080338D
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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom (c) http://www.st.com
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